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www.latticesemi.com 1 pac81_01 isppac81 in-system programmable analog circuit october 2001 data sheet features in-system programmable(isp?) analog ? instrument ampli er gain stage ? precision active filtering (10khz to 75khz) ? continuous-time fifth order low pass topology ? dual, a/b con guration memory ? non-volatile e 2 cmos ? cells ? ieee 1149.1 jtag serial port programming unique flexibility and performance ? programmable gain range (0db to 20db) ? implements multiple filter types: elliptical, chebyshev, butterworth ?l ow distortion (thd < -80db at 10khz) ?a uto-calibrated input offset voltage t rue differential i/o ? high cmr instrument ampli er input ? 2.5v common mode reference on chip ? rail-to-rail voltage outputs single supply 5v operation ?p ow er dissipation of 133mw ? 16-pin plastic soic, pdip packages applications include integrated ? single +5v supply signal conditioning ? programmable filters with fully differential i/o ? analog front ends, 12-bit data acq. systems ? dsp system front end signal conditioning ? high-performance reconstruction filters t ypical application diagram functional block diagram description the isppac81 is a member of the lattice family of in-system programmable analog circuits, digitally con gured via nonvol- atile e 2 cmos technology. analog building blocks, called pacell?(s), replace traditional analog components such as opamps, eliminating the need for e xternal resistors and capacitors. with no requirement for e xternal con guration components, isppac81 expedites the design process, simplifying prototype circuit implementation and change, while providing high-performance integrated functionality. with all components on chip, there is no longer a concern of performance degradation due to component mis- match or other external factors. the isppac81 provides reli- able and repeatable performance, every time. designers con gure the isppac81 and verify its performance using pac-designer ? , an easy-to-use, microsoft windows ? compatible program. a lter con guration database is pro- vided whereby thousands of different con gurations can be realized. no special understanding of lter synthesis is required beyond that of general speci cations such as corner frequency and stopband attenuation, etc. the software lists the possible choices that meet the designer?s speci cations which can then be loaded directly into either of two device (a/ b) con gurations from the lookup table. device programming is supported using pc parallel port i/o operations. the isppac81 is con gured through its ieee standard 1149.1 compliant serial port. the e xible in-system programming capability enables programming, veri cation and recon gura- tion, if desired, directly on the printed circuit board. vin vrefout a/b & gain spi control reference ain- ain+ 12-bit differential dsp input adc isppac81 5v 5v 5v out+ out? in+ in? vs vrefout test test e 2 cmos cfg a ref & auto-cal isp control e 2 cmos cfg b ia oa 5th order lpf 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 tdi tdo tck tms gnd cal enspi cs isppac81
lattice semiconductor isppac81 data sheet 2 dc electrical characteristics t a = 25c; v s = 5.0v; 1v < v out < 4v; gain = 1; output load = 200pf, 1m ? ? ? ? . filter con guration = cc055042, f p = 17.62khz; a uto-cal initiated immediately prior. (unless otherwise speci ed). symbol parameter condition min. typ. max. units analog input v in (1) input voltage range applied to either v in+ or v in- 14v v in-diff differential input voltage swing (2) 2 |v in+ - v in- |6 v p-p v os (2) differential offset voltage (input referred) g=10 g = 1 250 2.5 1,000 10 v mv ? v os / ? t differential offset voltage drift -40 to +85 c 100 v/ c r in input resistance 10 9 ? c in input capacitance 2pf i b input bias current at dc 1 pa e n input noise voltage density at 10khz, referred to input, g=10 71 analog output v out output voltage range present at either v out+ or v out- 0.1 4.9 v v out-diff differential output voltage swing (2) 2 |v out+ - v out- | 9.6 v p-p i out output current source/sink 10 ma v cm common mode output voltage (v out+ - v out- )/2 2.495 2.5 2.505 v static performance g programmable gain range individual gain ampli t er (1, 2, 5, 10) 0 20 db gain error r l = 300 ? differential 0.5 2.5 % ? g/ ? t gain drift -40 to +85 c 20 ppm/ c psr power supply rejection differential at 1khz single-ended at 1khz 80 67 db db common mode reference output (vref out ) vref out reference output voltage range nominally 2.500v -0.2 0.2 % reference output voltage drift -40 to +85 c5 0 ppm/ c iref out reference output current (vref out = 1%) source (vref out = 1%) sink 50 -350 a a reference output noise voltage 10mhz bandwidth 40 v rms reference power supply rejection 1khz 80 db programming erase/reprogram cycles 10k 1m cycles digital i/o v il input low voltage 0 0.8 v v ih input high voltage 2 v s v i il , i ih input leakage current 0v tck, enspi, cal input vs 0v tdi, mts, cs inputs vs -10/+40 -70/+10 a a v ol output low voltage (tdo) i ol = 4.0ma 0.5 v v oh output high voltage (tdo) i oh = -1.0ma 2.4 v nv/ hz
lattice semiconductor isppac81 data sheet 3 ac electrical characteristics symbol parameter condition min. typ. max. units dynamic performance (4) snr signal to noise (g=1 to 10) 0.1hz to 75khz, f c = 50khz 86 db thd total harmonic distortion (differential) single-ended (f p = 50khz) f in = 10khz, v in = 6v p-p f in = 10khz, v in = 6v p-p -80 -80 -72 -72 db db cmr common mode rejection (v in = 1v to 4v) note: v in+ and v in- connected together 10khz, f c = 50khz 48 60 db filter characteristics (4) |f c | absolute corner frequency accuracy deviation from calculated -3db point f c = 10khz or 50khz 0.8 % ? f c max delta between filters (computed) butterworth, 10khz to 60khz 0.6 3.6 % ? f c / ? t corner frequency delta vs. temperature f c = 10khz 0.03 %/ c ? f c / ? v corner frequency delta vs. supply voltage f c = 10khz 0.09 %/ v elliptic filter response (5) p assband ripple p assband ripple f c = 10khz f c = 50khz 1.4 1.5 db db po wer supplies v s operating supply voltage 4.75 5 5.25 v i s supply current v s = 5.0v 26.5 33 ma p d po w er dissipation v s = 5.0v 133 165 mw t emperature range operation -40 85 c storage -65 150 c notes: (1) a wider input range of 0.7v to 4.3v is typical, but not guaranteed. inputs larger than this will be clipped. input s ignals are also subject to common-mode voltage limitations. refer to the table of conditions in this data sheet. (2) refer to theory of operation secti on later in this data sheet for explanation of differential voltage swing computation. (3) to insure full spec performance an additional auto-calibra tion should be per- fo r med after initial turn-on and the device reaches thermal stability. (4) although many hundreds of thousands of lter con gurations are avail- able using isppac81, not every type will have corner frequencies available from exactly 10khz to 75khz, depending on the tables available from within pac-designer lter design tools. the general speci cations given under this heading are realized using the elliptic lter types. for more information on other types and/or frequencies not contained in the lter database, please contact lattice marketing. (5) a cauer elliptic l- ter of type cc051042 (see data sheet text) is used to guarantee these speci c lter accuracy speci cations. it is assumed that all other con g- urations available in pac-designer will exhibit equivalent performance according to the applicability of the individual lter type. necessary limitations will apply, however, when speci cations do not directly apply. see the data sheet text, application notes and guides in pac-designer f or speci c lter type considerations.
lattice semiconductor isppac81 data sheet 4 pin descriptions connection notes 1. all inputs and outputs are labeled with plus (+) and minus (-) signs. polarity is labeled for reference and can be selected externally by reversing pin connections. 2. all analog output pins are ?hard-wired? to internal output devices and should be left open if not used. v out+ and v out- should not be tied together as unnecessary power will be dissipated. 3. when the signal input is single-ended, the other half of the unused differential input must be connected to a dc common-mode reference (usually vref out , 2.5v). absolute maximum ratings supply voltage vs . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7v logic and analog input voltage applied. . . . . . . . . . . . . . . 0 to vs logic and analog output short circuit duration . . . . . . inde nite lead temperature (soldering, 10 sec.) . . . . . . . . . . . . . . . .260c ambient temperature with power applied . . . . . . . . -55 to 125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . -65 to 150c note: stresses above those listed may cause permanent damage to the device. these are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this speci cation is not implied. pin(s) symbol name description 1 tms t est mode select serial interface logic mode select pin (input). jtag interface mode only. 2 tck test clock serial interface logic clock pin (input). jtag and spi interface modes. 3 tdi t est data in serial interface logic pin (input) for both jtag and spi opera- tion modes. 4 tdo test data out serial interface logic pin (output) for both jtag and spi opera- tion modes. input data valid on falling edge of tck (jtag), or on rising edge of cs (spi). 5 cs chip select chip select logic input pin. spi data latch. 6 cal auto-calibrate digital pin (input). commands an auto-calibration sequence on a rising edge. 7 enspi enable spi mode enable spi logic input pin. when high, causes serial port to run in spi mode. 8 gnd ground ground pin. should normally be connected to the analog g round plane. 9 vrefout common-mode reference common-mode voltage reference output pin (+2.5v nominal). must be bypassed to gnd with a 1 f capacitor. 10, 11 in inputs (+ or -) differential input pins, using two pins (e.g., in+ and in-). plus or minus components of v in , where differential v in = v in+ - v in- . 12, 15 test test pin test pin. connect to gnd for proper circuit operation. 13, 14 out outputs (+ or -) differential output pins, using two pins (e.g., out+ and out-). complementary with respect to vrefout. differential v out = v out+ - v out -. 16 vs supply voltage analog supply voltage pin (5v nominal). should be bypassed to gnd with 1 f and .01 f capacitors.
lattice semiconductor isppac81 data sheet 5 pa rt number description isppac81 ordering information pa ck ag e options pa rt number package ISPPAC81-01PI 16-pin pdip isppac81-01si 16-pin soic device number isppac81 ? xx x x grade blank = commercial i = industrial performance grade 01 = standard package p = pdip s = soic device family 16-pin soic isppac81 16-pin pdip 1 1 isppac 81
lattice semiconductor isppac81 data sheet 6 timing speci cations (jtag interface mode) t a = 25c; v s = +5.0v (unless otherwise speci ed) *note: during device jtag programming, analog output response will deviate from expected behavior. this is because all con guration information is erased and then re-written as part of a normal programming cycle, momen- tarily changing device lter and gain parameters. behavior will deviate from that expected during both of these steps since the analog outputs are not clamped during a programming cycle. during erase, a drop in the lter cor- ner frequency and an automatic change to the 10x gain setting can be expected (80ms minimum by speci cation) and will continue until bits go to their nal state after a jtag write command is issued (less than 2ms later, though the write cycle must still be maintained for a full 80ms to achieve speci ed data retention). symbol parameter condition min. typ. max. units dynamic performance tckmin minimum clock period 200 ns tckh tck high time 50 ns tckl tck low time 50 ns tmss tms setup time 15 ns tmsh tms hold time 10 ns tdis tdi setup time 15 ns tdih tdi hold time 10 ns tdozx tdo oat to valid delay 60 ns tdov tdo valid delay 60 ns tdoxz tdi valid to oat delay 60 ns tpwp time for a programming operation executed in run-test/idle 80 100 ms tpwe time for an erase operation executed in run-test/idle 80 100 ms tpwcal1 time for auto-cal operation on power-up automatically executed at power-up 250 ms tcalmin minimum auto-cal pulse width 40 ns tpwcal2 time for user-initiated auto-cal operation executed on rising edge of cal 100 ms cal (note: cal internally initiated at device turn-on.) v out+ = v out? = 0 v out tpwcal1, tpwcal2 tcalmin tmss tmss tck tms tpwp, tpwe *(prgusr/ube executed in run-test/idle state) tckmin tckh tckl tmss tdis tmsh tdih tdozx tdov tdoxz tck tms tdi tdo
lattice semiconductor isppac81 data sheet 7 timing speci cations (spi interface mode) t a = 25c; v s = +5.0v (unless otherwise speci ed) symbol parameter condition min. typ. max. units dynamic performance tckmin minimum clock period 200 ns tckh tck high time 100 ns tckl tck low time 100 ns tcss cs setup time 20 ns tcsminhi minimum cs pulse widths 40 ns tdis tdi setup time 15 ns tdih tdi hold time 10 ns tdozx tdo oat to valid delay 60 ns tdov tdo valid delay 60 ns tdoxz tdo valid to oat delay 60 ns tckmin tcsminhi tckl tckh tcss tdis tdih tdozx hi-z hi-z tdov tdoxz tck cs tdi tdo
lattice semiconductor isppac81 data sheet 8 t ypical performance characteristics noise voltage (nv hz) power supply rejection (db ) input noise spectrum thd vs. frequency v os te mpco filter variation (3 sigma) cmr vs. frequency psr vs. frequency frequency (hz) 10 100 1k 10k 100k 1m frequency (hz) 30 40 50 60 70 80 90 common mode rejection (db) elliptical filter cc055042 fc = 50khz elliptical filter cc055042 fc = 18khz 100 1k 10k 100k 1m f requency (hz) 40 30 50 60 70 80 90 1k 10k 100k frequency (hz) -95 -100 -90 -85 -80 -75 -70 to t a l harmonic distortion (db) -80 db -40 db 0 db percentage of devices (%) 10khz 100khz 1mhz stopband attenuation variation over process < 1.5db elliptical filter cc055042 passband ripple variation over process < 0.20db elliptical filter cc055042 fc = 50khz g = 1 g = 10 5 0 10 15 20 25 35 offset tempco ( v/c) -240 -120 0 120 240 pdip pkg -40c to +85c 30 1 10 100 1k 10k 100k 1m 100 10 1k g = 10 (referred to input) butterworth fc = 50khz 1
lattice semiconductor isppac81 data sheet 9 theory of operation reference con guration in the speci cations table, speci c lter con gurations are referred to, such as the cc055042 at 17.62khz. this is simply a shorthand notation for the classical lter type that includes all the characteristic parameters of the particu- lar con guration. in this case, the cc refers to complete chebyshev, or a chebyshev ripple response in both the pass and stopbands of the lter. another common name for this type of lter is the elliptic family of lters. the next set of numbers, ?05? refers to the order of the lter. in the case of isppac81 this will always be fth order. the next two digits signify the re ection coef cient (rf), in this case 10%, and has a direct mathematical relationship to the passband ripple magnitude of the lter, where the passband ripple expressed in db = 10*log(1-rf 2 ). the nal two digits are the passband to stopband attenuation ratio expressed as an angle, in this case 42 degrees or 1.49 (1/ sin(( /180)*42)). this con guration corresponds to the elliptical lter with the id# 1088 (fp=17.62khz; fc=17.96khz) in the lter con guration database utility of pac-designer. because of the almost limitless number of con gurations realizable with isppac81, standard test con gurations had to be chosen. the elliptical family was chosen since it has many parameters that can be easily and directly measured to insure that all the internal circuits of isppac81 are operating correctly. figure 1. simpli?d isppac81 filter core schematic a1 a3 a4 a5 a1 a2 c1 l2 c3 l4 c5 c231 c213 c435 c453 r11 20k r55 40k r21 20k r32 -20k r43 20k r54 -40k r12 -20k r23 20k r34 -20k r45 20k v in v out v4 v3 v2 v1 rin 20k g = 1/20k; g/2 = 1/40k; c2 = c231 = c213; c4 = c435; c4/2 = c453 v out v in -g(l l c c) s ((l g c g l c ) s g s s = ++ + + ++ + ++ + 22442 4 2 2 2 2 44 24 5 4 )( ) ( )( ) -(l2 c4 2 l4 c1) 2(l2 c1 c3 l4 c5) - 2(c2 2 l2 l4 c5) -(l2 g c4 2 l4) l2 c1 c3 l4 g) - (c2 2 l2 l4 g) 2(l2 g c3 l4 c5) (l2 c1 c3 g 2 l2 g 2 c3 l4) - (g 2 l4 c4 2 2(g 22 l4 c5 c3) - 4(g 2 l4 c5 c2) 2(l2 c5 g 3 )- 2(g 3 l4 c2) g 3 l4 c3) l2 g 3 c1) 2(g 3 l4 c5) - 2( l2 c4 g 3 g 3 c1 l4) l2 c3 g 3 ) s 2 2(g 4 c5) g ++ ++++++ ++ -l c c g g c l c l c g c - c l g s 22 14 2 2 2 14 5 2 2 5 2 12 2 2 23 ()()() () (( )(( ( 44 c3) - 2(g 4 c4) g 4 l4) g 4 c1) l2 g 4 )- 2(g 4 c2) s 2 g 5 ++ + + (( (
lattice semiconductor isppac81 data sheet 10 spi power-on condition the spi shift register is always reset to all zeroes when an isppac81 powers on. that means that if the enspi pin is high at power on, the initial con guration will be set to a gain of 1x (0db) and con guration ?a? is selected as the ?wake-up? con guration. the only way to prevent this behavior would be to hold the enspi pin low while applying power to the device. because this is usually impractical, it is advised that if the isppac81 is used in spi mode that it be reloaded to the desired rst con guration every time power is cycled to the device and/or that the ?a? con gu- r ation memory hold the desired ?wake up? lter response. a/b con guration tw o complete con gurations can be stored in the e 2 memory of the isppac81. selection of either the ?a? or ?b? con guration in real time is accomplished with the device in the spi interface mode (enspi pin = logic high). an eight-bit string is read into the isppac81 in the following order: four ?don?t care? bits followed by a cal command bit, the a/b con guration setting and gain bits pg2 and pg1. ta b le 1. spi control bit sequence ta b le 2. gain bit settings ta b le 3. jtag user con?uration bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pg2 pg1 a/b cal xxxx gain setting pg2 pg1 1x (0db) 0 0 2x (6db) 0 1 5x (14db) 1 0 10x (20db) 1 1 symbol name description f reqrange bit hi/lo frequency range bit depending on the corner frequency, the frequency range bit is automatically set from within pac-designer to optimize the transfer function response of the isppac81. exists for both the a and b user strings. can be overridden from within pac-designer from the edit symbol dialog. ues bits user electronic signature these are uncommitted e 2 bits that can be used to store device information for future reference. the isppac81 contains 21 ues bits. these bits are accessible from within pac-designer by using the edit symbol, ues bits command. part of user con guration string a only. cap bits capacitor selection bits varying length data words for each of the seven con guration capacitors of the isppac81. there is a complete set of 70 bits total for each user con guration string, a and b. a/b bit initial con guration select with the a/b bit set to ?a? (a logic 0), the device will power up in the con gura- tion stored in user string a. the designations of a or b would have been deter- mined initially in the design environment using pac-designer. it is also possible to designate the b user string as the initial or ?wake up? con guration, although this is not recommended as it blocks the algorithm required to do a ?blind? veri- cation of the a con guration of a previously programmed device. this is deter- mined from within pac-designer in the edit symbol dialog. pg1 & pg2 bits programmable gain bits contained only in the a con guration string. can also be modi ed under spi control. refer to table 2 for bit setting speci cs. esf electronic security fuse setting this bit causes all subsequent readouts of the device con guration to be disabled (jtag verify commands). can be reset by performing a jtag user (usra) bulk erase commands and reprogramming the device. this feature is used to prevent unauthorized readout of the device?s con guration.
lattice semiconductor isppac81 data sheet 11 jtag user bits there are a number of user-con gured e 2 bits that control various aspects of and can all be accessed in either the pull-down menus or directly in the schematic design entry screen of the pac-designer software interface to the isppac81. see the online help associated with the isppac81 in pac-designer for more details of how to set/pro- gr am various operation modes. the list of control e 2 bits available is listed in table 3. differential i/o differential peak-peak voltage is determined by knowing the signal extremes on both differential input or output pins. for example, if v(+) equals 4v and v(-) equals 1v, the differential voltage is de ned as v(+) - v(-) = vdiff, or 4v - 1v = +3v. since either polarity can exist on differential i/o pins, it is also possible for the opposite extreme to e xist and would mean when v(+) equals 1v and v(-) equals 4v, the differential voltage is now 1v - 4v = -3v. to cal- culate the differential peak-peak voltage or full signal swing, the absolute difference between the two extreme vdiff?s is calculated. using the previous examples would result in |(+3v) - (-3v)| = 6v. it can be immediately seen that true differential signals result in a doubling of usable dynamic range. for more explanation of this and other dif- f erential circuit bene ts, please refer to application note number an6019, differential signaling. single-ended input to connect the isppac81 differential input to a single-ended signal, one of the differential inputs needs to be con- nected to a dc bias, preferably vref out . the input signal must either be ac coupled or have a dc bias equal to the dc level of the other input. since the input voltage is de ned as v in+ - v in- , the common mode level is ignored. the signal information is only present on one input, the other being connected to a voltage reference. single-ended output connecting the output to a single-ended circuit is simpler still. simply connect one-half of the differential output, but not the other. either output conveys the signal information, just at half the magnitude of the differential output. the dc level of the single-ended output will be vref out . if the load is not ac coupled and is at a dc potential other than vref out , the load draws a constant current. using one of the differential outputs halves the available output v oltage swing (3vp-p versus 6vp-p). if the load requires dc current, the available voltage swing is reduced. the output is capable of 10ma, so any dc current raises the minimum allowable load impedance. input common-mode voltage range f or the isppac81, both maximum input signal range and corresponding common-mode voltage range are a func- tion of the input gain setting. the maximum input voltage times the gain of an individual pacblock cannot exceed the output range of that block or clipping will occur. the maximum guaranteed input range is 1v to 4v, with a typical r ange of 0.7v to 4.3v for a 5v supply voltage. the input common-mode voltage is v cm = (v cm+ + v cm- )/2. when the value of v cm is 2.5v, there are no further input restrictions other than the previously mentioned clipping consideration. this is easily achieved when the input signal is true differential and referenced to 2.5v. when v cm is not 2.5v and the gain setting is greater than one, distortion will occur when the maximum input limit is reached for a particular gain. the lowest v cm f or a given gain setting is expressed by the formula, v cm? = 0.675v + 0.584gv in where g is the gain setting and v in is the peak input voltage, expressed as |v in+ - v in? | and the highest v cm is v cm+ = 5.0v - v cm? where 5v is the nominal supply voltage. in table 4, the maximum v in f or a given v cm? to v cm+ r ange is given. if the maximum v in is known, nd the equiv- alent or greater value under the appropriate gain column and the widest range for v cm will be found horizontally across in the left-most two columns. only a v cm r ange equal to or less than this will give distortion-free perfor- mance. conversely, if the maximum v cm r ange is known, the largest acceptable peak value of v in can be found in the corresponding gain column. all values of v in less than this will give full rated performance.
lattice semiconductor isppac81 data sheet 12 ta b le 4. input common-mode voltage range limitations software-based design environment design entry software designers con gure the isppac81 and verify its performance using pac-designer, an easy-to-use, microsoft win- dows compatible program. circuit designs are entered graphically and then veri ed, all within the pac-designer environment. full device programming is supported using pc parallel port i/o operations and a download cable connected to the serial programming interface of the isppac81. a database of lter con gurations is included with thousands of possible implementations to choose from. in addition, comprehensive on-line and printed documenta- tion is provided that covers all aspects of pac-designer operation. the pac-designer schematic window, shown in figure 2, provides access to all con gurable isppac81 elements via its graphical user interface. all analog input and output pins are represented. static or non-con gurable pins such as power, ground, vref out , and the serial digital interface are omitted for clarity. any element in the sche- matic window can be accessed via mouse operations as well as menu commands. when completed, con gura- tions can be saved, simulated, and downloaded to devices. pa c-designer operation can be automated and extended by using custom-designed visual basic? programs that set the interconnections and the parameters of isppac products. more information on this and other topics is included in the on-line documentation as well as the pa c-designer getting started manual. design simulation capability a powerful feature of pac-designer is its simulation capability, enabling quick and accurate veri cation of circuit operation and performance. once a circuit is con gured via the interactive design process, gain and phase response between any input and output can then be determined. this function is part of the simulator capability which derives a transfer equation between the two points and then sweeps it over the user-speci ed frequency r ange. figure 3 shows a typical screen plot of the gain/phase simulator. in it are the input to output response curves of an elliptical and a butterworth response stored in con guration a and b respectively. these are the two options speci ed in the design screen window shown in figure 2. input voltage magnitude (volts-peak) v cm- v cm+ g=1 g=2 g=5 g=10 1.000 4.000 0.557 0.278 0.111 0.056 1.100 3.900 0.728 0.364 0.146 0.073 1.200 3.800 0.899 0.450 0.180 0.090 1.300 3.700 1.071 0.535 0.214 0.107 1.400 3.600 1.242 0.621 0.248 0.124 1.500 3.500 1.413 0.707 0.283 0.141 1.600 3.400 1.584 0.792 0.317 0.158 1.700 3.300 1.756 0.878 0.351 0.176 1.800 3.200 1.927 0.964 0.385 0.193 1.900 3.100 2.098 1.049 0.420 0.210 2.000 3.000 2.270 1.135 0.454 0.227 2.100 2.900 2.441 1.220 0.488 0.244 2.200 2.800 2.612 1.306 0.522 0.261 2.300 2.700 2.783 1.392 0.557 0.278 2.400 2.600 2.955 1.477 0.591 0.295 2.426 2.574 3.000* 1.500* 0.600* 0.300* 2.500 2.500 3.126 1.563 0.625 0.313 *peak input voltage for guaranteed performance at a given gain setting.
lattice semiconductor isppac81 data sheet 13 the simulator is capable of displaying up to four separate input to output responses. this allows multiple signals to be viewed as well as intermediate results of component changes so performance comparisons can be made. there is also a user-positioned crosshair cursor that intersects the curves on the plot, and reads out the gain and frequency in the lower right hand corner of the plot window when activated. figure 2. initial pac-designer schematic design entry screen figure 3. pac-designer simulation plot screen pac designer - [isppac81.pac: plot ] read y file edit view tools options window help 42.553 pf 3.623 pf 16.732 pf 61.759 pf 9.974 pf 13.564 pf 21.941 pf ues bits = 000000000000000000000 wak eup = cfg a ia 2 3.306 pf 0.000 pf 8.548 pf 10.595 pf 0.000 pf 8.663 pf 1.655 pf isppac81 cfg a cfg b c1 c2 l2 c3 c4 l4 c 5 cfga type = elliptical fc = 17.96khz fs = 26.35khz pb ripple = -1.26db sb atten = -54.78db filter id = 1088 cfgb type = bu tterworth fc = 60.02khz fs = pb ripple = sb at ten = filter id = 282 in out oa 5th order low-pass filter pacell pac desig ner - [isppac81.pac: schematic ] read y file edit view tools options window help 0 -20 -40 -60 -80 -100 -120 0 10 100 1k 10k 100k 1m 10m 38.1 0 -50 -100 -150 -200 -250 -300 0 10 100 1k 10k 100k 1m 10m gain plot phase plot
lattice semiconductor isppac81 data sheet 14 in-system programmability in-system programming the isppac81 is an in-system programmable device. this is accomplished by integrating all high voltage program- ming circuitry on-chip. programming is performed through a 5-wire, ieee 1149.1 compliant serial port interface at normal logic levels. once a device is programmed, all con guration information is stored on-chip, in non-volatile e 2 cmos memory cells. the speci cs of the ieee 1149.1 serial interface are described in the interface section of this data sheet. user electronic signature a user electronic signature (ues) feature is included in the e 2 memory of the isppac81. it contains 21 bits that can be con gured by the user to store unique data such as id codes, revision numbers or inventory control data. electronic security an electronic security ?fuse? (esf) bit is provided in every isppac81 device to prevent unauthorized readout of the e 2 cmos user bit patterns. once programmed, this cell prevents further access to the functional user bits in the device. this cell can only be erased by reprogramming the device, so the original con guration can not be exam- ined once programmed. usage of this feature is optional. production programming support once a nal con guration is determined, an ascii format jedec le is created using the pac-designer software. devices can then be ordered through the usual supply channels with the user?s speci c con guration already pre- loaded into the devices. by virtue of its standard interface, compatibility is maintained with existing production pro- gr amming equipment, giving customers a wide degree of freedom and e xibility in production planning. evaluation fixture included in the basic isppac81 design kit is an engineering prototype board that can be connected to the parallel port of a pc. it demonstrates proper layout techniques for the isppac81 and can be used in real time to check cir- cuit operation as part of the design process. input and output connections as well as a ?breadboard? circuit area are provided to speed debugging of the circuit. figure 4. con?uring the isppac81 ?n-system from a pc parallel port ispdownload cable (6') 4 other system circuitry isppac81 device pa c-designer software
lattice semiconductor isppac81 data sheet 15 ieee standard 1149.1 interface serial port programming interface communication with the isppac81 is facilitated via an ieee 1149.1 test access port (tap). it is used by the isppac81 as a serial programming interface, and not for boundary scan test purposes. there are no boundary scan logic cells in the isppac81 architecture. this does not prevent the isppac81 from functioning correctly, how- ev er, when placed in a valid serial chain with other ieee 1149.1 compliant devices. a brief description of the isppac81 serial interface follows. for complete details of the reference speci cation, refer to the publication, standard test access port and boundary-scan architecture, ieee std 1149.1-1990 (which now includes ieee std 1149.1a-1993). overview an ieee 1149.1 test access port (tap) provides the control interface for serially accessing the digital i/o of the isppac81. the tap controller is a state machine driven with mode and clock inputs. under the correct protocol, instructions are shifted into an instruction register which then determines subsequent data input, data output, and related operations. device programming is performed by addressing the user register, shifting data in, and then ex ecuting a program user instruction, after which the data is transferred to internal e 2 cmos cells. it is these non- v olatile cells that determine the con guration of the isppac81. by cycling the tap controller through the necessary states, data can also be shifted out of the user register to verify the current isppac81 con guration. instructions e xist to access all data registers and perform internal control operations. f or compatibility between compliant devices, two data registers are mandated by the ieee 1149.1 speci cation. others are functionally speci ed, but inclusion is strictly optional. finally, there are provisions for optional data reg- isters de ned by the manufacturer. the two required registers are the bypass and boundary-scan registers. for isppac81, the bypass register is a one-bit shift register that provides a short path through the device when bound- ary testing or other operations are not being performed. the isppac81, as mentioned, has no boundary scan logic and therefore no boundary scan register. all instructions relating to boundary scan operations place the isppac81 in the bypass mode to maintain compliance with the speci cation. the optional identi cation register described in ieee 1149.1 is also included in the isppac81. one additional data register included in the tap of the isppac81 is the lattice de ned user register. figure 5 shows how the instruction and various data registers are placed in an isppac81. figure 5. isppac81 tap registers bypass register mux instruction register test access port (tap) logic id register user register tdi tdo tck tms output latch
lattice semiconductor isppac81 data sheet 16 t ap controller speci cs the tap is controlled by the test clock (tck) and test mode select (tms) inputs. these inputs determine whether an instruction register or data register operation is performed. driven by the tck input, the tap consists of a small 16-state controller design. in a given state, the controller responds according to the level on the tms input as shown in figure 6. test data in (tdi) and tms are latched on the rising edge of tck, with test data out (tdo) becoming valid on the falling edge of tck. there are six steady states within the controller: test-logic-reset, run- t est/idle, shift-data-register, pause-data-register, shift-instruction-register and pause-instruction-register. but there is only one steady state for the condition when tms is set high: the test-logic-reset state. this allows a reset of the test logic within ve tcks or less by keeping the tms input high. test-logic-reset is the power-on default state. figure 6. test access port (tap) controller state diagram when the correct logic sequence is applied to the tms and tck inputs, the tap will exit the test-logic-reset state and move to the desired state. the next state after test-logic-reset is run-test/idle. until a data or instruction scan is performed, no action will occur in run-test/idle (steady state = idle). after run-test/idle, either a data or instruction scan is performed. the states of the data and instruction register blocks are identical to each other dif- fe r ing only in their entry points. when either block is entered, the rst action is a capture operation. for the data registers, the capture-dr state is very simple: it captures (parallel loads) data onto the selected serial data path (previously chosen with the appropriate instruction). for the instruction register, the capture-ir state will always load the idcode instruction. it will always enable the id register for readout if no other instruction is loaded prior to a shift-dr operation. this, in conjunction with mandated bit codes, allows a ?blind? interrogation of any device in a compliant ieee 1149.1 serial chain. f rom the capture state, the tap transitions to either the shift or exit1 state. normally the shift state follows the capture state so that test data or status information can be shifted out or new data shifted in. following the shift state, the tap either returns to the run-test/idle state via the exit1 and update states or enters the pause state via exit1. the pause state is used to temporarily suspend the shifting of data through either the data or instruction register while an external operation is performed. from the pause state, shifting can resume by reentering the t est-logic-rst run-test/idle select-dr-scan select-ir-scan capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir p ause-dr pause-ir exit2-dr exit2-ir update-dr update-ir 1 0 00 00 00 11 00 00 11 11 00 11 00 11 11 11 1 0 note: the value shown adjacent to each state transition in this figure represents the signal present at tms at the time of a rising edge at tck.
lattice semiconductor isppac81 data sheet 17 shift state via the exit2 state or be terminated by entering the run-test/idle state via the exit2 and update states. if the proper instruction is shifted in during a shift-ir operation, the next entry into run-test/idle initiates the test mode (steady state = test). this is when the device is actually programmed, erased or veri ed. all other instructions are executed in the update state. t est instructions like data registers, the ieee 1149.1 standard also mandates the inclusion of certain instructions. it outlines the function of three required and six optional instructions. any additional instructions are left exclusively for the manu- f acturer to determine. the instruction word length is not mandated other than to be a minimum of two bits, with only the bypass and extest instruction code patterns being speci cally called out (all ones and all zeroes respec- tively). the isppac81 contains the required minimum instruction set as well as one from the optional instruction set. in addition, there are several proprietary instructions that allow the device to be con gured and veri ed. for isppac81, the instruction word length is ve bits. all isppac81 instructions available to users are shown in table 5. ta b le 5. isppac81 tap instructions bypass is one of the three required instructions. it selects the bypass register to be connected between tdi and tdo and allows serial data to be transferred through the device without affecting the operation of the isppac81. the bit code of this instruction is de ned to be all ones by the ieee 1149.1 standard. the required sample/preload instruction dictates the boundary-scan register be connected between tdi and tdo. the isppac81 has no boundary-scan register, so for compatibility it defaults to the bypass mode when- ev er this instruction is received. the bit code for this instruction is de ned by lattice as shown in table 5. the extest (external test) instruction is required and would normally place the device into an external boundary test mode while also enabling the boundary-scan register to be connected between tdi and tdo. again, since the isppac81 has no boundary-scan logic, the device is put in the bypass mode to ensure speci cation compati- bility. the bit code of this instruction is de ned by the 1149.1 standard to be all zeros. the optional idcode (identi cation code) instruction is incorporated in the isppac81 and leaves it in its functional mode when executed. it selects the device identi cation register to be connected between tdi and tdo. the identi cation register is a 32-bit shift register containing information regarding the ic manufacturer, device type and version code (see figure 7). access to the identi cation register is immediately available, via a tap data scan operation, after power-up of the device, or by issuing a test-logic-reset instruction. the bit code for this instruction is de ned by lattice as shown in table 5. instruction code description extest 00000 external test. default to bypass. addusr 00001 address user data register (a or b). abe 00010 user a bulk erase. bbe 00011 user b bulk erase. vera 00100 ve r ify user a data register. verb 00101 ve r ify user b data register. prga 00110 program user a data register. prgb 00111 program user b data register. encal 01100 enable calibration sequence. idcode 01101 read identi cation data register. sample 11110 sample/preload. default to bypass. bypass 11111 bypass (connect tdi to tdo).
lattice semiconductor isppac81 data sheet 18 figure 7. identi?ation code (idcode) 32-bit binary word for lattice isppac81 addusr (address user register) instruction is a lattice-de ned instruction that selects the user register to be shifted during a shift-dr operation. normal operation of a device is not interrupted by this instruction. it precedes a prga or prgb (program user a or b) instruction to shift in a new con guration from the user register into either the a or b con guration memory, and follows a vera or verb (verify user a or b) instruction to shift out the cur- rent con guration of either a or b con guration memory into the user register. the bit code for this instruction is shown in table 5. the prga and prgb (program user a or b) are lattice instructions that enable the data shifted into the user reg- ister to be programmed into the non-volatile e 2 cmos memory of the isppac81 and thereby alter either or both of its two user con gurations. the user register is a 96-bit shift register that contains all the user-controlled parametric data pertaining to the con guration of the isppac81. note: although the user register length is 96 bits, only the ?a? con guration is that long. the device gain setting bits, ues bits, and security fuse bit are all part of the ?a? con gu- r ation memory and are not stored at all in ?b? memory, which only contains the unique capacitor settings of that con guration. when initially programming or reprogramming the isppac81 with software other than pac-designer, or an authorized third-party programmer (e.g., via microcontroller, refer to the lattice application note covering the required algorithms necessary for complete jtag device programming control of the isppac81, speci c bit assign- ments, word lengths, etc.). normal operation of the device is interrupted during the actual programming time. a programming operation does not begin until entry of the run-test/idle state. the time required to insure data reten- tion is given in the tap signal speci cations table. the user must ensure that the recommended programming times are observed. the bit code for these instructions is shown in table 5. vera and verb (verify user a or b) are the next lattice instructions and cause the current a or b con gurations of the isppac81 to be loaded into the user register. this operation doesn?t interrupt operation of the device. the current con guration of either the a or b con guration memory can then be shifted out of the user register immedi- ately after an addusr instruction is executed. note: the veri cation of memory con guration ?a? is possible only when the a/b bit is set to a logic 0. this must be taken into account if verify will be performed at a later time on parts with unknown con gurations (refer to the lattice application note covering the required algorithms necessary f or complete jtag device programming control of the isppac81, speci c bit assignments, word lengths, etc.). if the a/b bit has been set to a logic 1, it will not be possible to do a vera command properly. the bit code for this instruction is shown in table 5. encal (enable calibration) is a lattice instruction that enables the start of an auto-calibration sequence. this operation causes all outputs of the device to go to 2.5v until the calibration sequence is completed (see timing speci cations). as with the programming instructions above, calibration does not begin until entry of the run-test/ idle state. the completion of the calibration is not dependent, however, on any further tap control. this means the state of the tap can be returned immediately to the test-logic-reset state. the only consideration would be to not clock the tap during critical analog operations. the rst several milliseconds of the calibration routine are con- sumed waiting for con gurations to settle, though, leaving more than enough time to clock the tap back to the test- logic-reset state. the bit code for this instruction is shown in table 5. the last lattice instructions are abe and bbe (user a or b bulk erase). operation of the device is interrupted dur- ing an abe or bbe, during which all inputs are disconnected and all outputs driven to vref out (2.5v). to econo- mize internal circuitry, programming can only be selectively done in one direction (from zeroes to ones). the abe msb xxxx / 0000 0001 0010 0001 / 0000 0100 001 / 1 lsb vers ion (4 bits) e 2 configured part number (16 bits) 0121h = pac81 jedec manfacturer identity code for lattice semiconductor (11 bits) constant 1 (1 bit) per 1149.1-1990
lattice semiconductor isppac81 data sheet 19 and bbe are used to return all user bits to a zero state at the same time. an abe or bbe usually proceeds a prga or prgb operation, otherwise one to zero changes would not be implemented. it can also be used to erase all con- guration information from a device and is the default condition of parts shipped from the factory. the same pro- gr amming time constraints apply to abe and bbe as for prga and prgb. the bit code for this instruction is shown in table 5. the addusr, bypass, extest, idcode and sample/preload instructions are all executed in the update- ir state. other instructions: prgusr, verusr and ube are executed upon entry of the run-test/idle state. it is recommended that when all serial interface operations are completed, the tap controller be reset and left in the test-logic-reset state (the power-up default) and the tck and tms inputs idled. this will insure the best ana- log performance possible by minimizing the effects of digital logic ?feed-through.?
lattice semiconductor isppac81 data sheet 20 pa ck ag e diagrams 16-pin plastic pdip dimensions in inches min./max. dimensions in millimeters, shown in parenthesis, are for reference only. 16-pin plastic soic dimensions in inches min./max. dimensions in millimeters, shown in parenthesis, are for reference only. .008 / .012 (.20 / .31) 0-15 .195 (4.95) max .015 /.022 (.38 / .56) .055 /.065 (1.40 / 1.65) .745 / .755 (18.92 / 19.18) .300 / .325 (7.61 / 8.25) .240 / .260 (6.10 / 6.60) .100 (2.54) bsc .125 / .135 (3.17 / 3.43) .015 (.38) min 0 8 .024 (.61) .040 (1.02) .292 (7.42) .299 (7.59) .400 (10.16) .410 (10.41) .014 (.35) .019 (.48) .050 (1.27) bsc .402 (10.21) .412 (10.46) .0091 (.23) .0125 (.32) .097 (2.46) .104 (2.64) .0050 (.127) .0115 (.292)

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